1. Field of the Invention
The present invention relates to a voltage level shifter. Such a shifter may, for example, be used in large area silicon-on-insulator (SOI) circuits for interfacing with signals of smaller amplitudes. An example of such an application is monolithic driver circuitry for flat-panel matrix displays, such as liquid crystal displays, fabricated with low temperature poly-silicon thin-film transistors (TFTs) where interfacing between signal levels of 3.3 to 5 volts and signals of 10 to 20 volts is often required. The present invention also relates to a poly-silicon display.
2. Description of the Related Art
FIG. 1 of the accompanying drawings illustrates a basic CMOS inverter which may be used as a simple voltage level shifter. The inverter comprises a P-type transistor T1 and an N-type transistor T2 whose drains are connected together and whose sources are connected to a supply line vdd and ground gnd, respectively. The gates of the transistors T1 and T2 are connected together and to an input terminal IN and the drains of the transistors T1 and T2 are connected together to an inverting output !OUT. The input signals can swing about the inverter switch point between logic levels which are less than the voltages defined by the supply line vdd and ground gnd. The inverter can operate as a level shifter because the output swings between voltage levels which are almost equal to the voltages of the supply line vdd and ground gnd. However, in practice, the degree of level shifting is relatively small because voltages close to the inverter switch point result in simultaneous and undesirable (above threshold) conduction of the transistors T1 and T2. The condition for this not to occur is that:
|xcex94VIN| greater than VDDxe2x88x92VTnxe2x88x92|VTp|
where VDD is the voltage on the supply line vdd and VTn and VTp are the threshold voltages of the N-type and P-type transistors, respectively.
FIG. 2 of the accompanying drawings illustrates another type of single input level shifter for low input voltages, for example as disclosed in U.S. Pat. No. 4,707,623. The shifter comprises a first circuit branch comprising a first P-type transistor T1 and a second N-type transistor T2 with their drains connected together to an inverting output !OUT and their sources connected to a supply line vdd and ground gnd, respectively. The level shifter comprises a second circuit branch comprising third and fourth P-type transistors T3 and T4. The source of the third transistor T3 is connected to the supply line vdd whereas the drain of the fourth transistor T4 is connected to ground gnd. The drain of the transistor T3 is connected to the source of the transistor T4 and to the gate of the transistor T2. An input IN is connected to the gates of the transistors T1 and T4. A bias voltage input Vb is connected to the gate of the transistor T3.
The transistors T3 and T4 are connected as a source follower whose output voltage is approximately given by VIN+(VDDxe2x88x92Vb) when the transistors T3 and T4 are matched and are in saturation. The input signal drives the gate of the transistor T1 directly whereas the output of the source follower drives the gate of the transistor T2 with a copy of the input signal which is shifted in the positive direction by (VDDxe2x88x92Vb). These voltage levels are sufficient to switch the transistors T1 and T2, which operate as push-pull devices with high state logic input levels which are substantially lower than the supply voltage and low state logic input levels which are substantially equal to ground potential.
FIG. 3 of the accompanying drawings illustrates a level shifter of the type disclosed in GB 9905041.1. The level shifter illustrated in FIG. 3 is similar to that shown in FIG. 2 and will be described in detail only in so far as it differs therefrom. In particular, the source of the second transistor T2 is connected to a second inverting input !IN which receives an inverted input signal i.e. a signal which is the logical complement of the direct input signals supplied to the input IN.
During operation of the level shifter of FIG. 3, when the input IN is high and the input !IN is low, the level shifter behaves as described hereinbefore for the level shifter of FIG. 2. The output !OUT is thus pulled low. When the input IN goes low and the input !IN goes high, the first transistor T1 is strongly turned on and tries to pull the output !OUT high. The source follower formed by the third and fourth transistors T3 and T4 drives the gate of the transistor T2 with a voltage which is lower than the supply voltage VDD but which is sufficient to turn the transistor T2 on. The high logic input signal at the input !IN is supplied to the source of the transistor T2 and thus reduces the gate-source voltage thereof so that the gate over-drive and pull-down capability at the output !OUT is restricted. Consequently, the output !OUT is pulled up more easily by the action of the first transistor Ti. This results in a larger output swing compared with that produced by the level shifter shown in FIG. 2.
According to a first aspect of the invention, there is provided a voltage level shifter comprising: a first input for receiving a direct input signal; a second input for receiving an inverted input signal; an output for producing an inverted output signal which is inverted and level-shifted relative to the direct input signal; a voltage follower whose input is connected to the first input; and an output circuit comprising a first transistor of a first conduction type whose output electrode is connected to the output and whose control electrode is connected to an output of the voltage follower, and a second transistor of a second conduction type different from the first type whose output electrode is connected to the output, whose control electrode is connected to the output of the voltage follower, and whose common electrode is connected to the second input.
The voltage follower may comprise third and fourth transistors of the first conduction type whose main conduction paths are connected in series between first and second power supply inputs, the control electrode of the fourth transistor being connected to the first input and the control electrodes of the first and second transistors being connected to the output electrode of the third transistor and to the common electrode of the fourth transistor.
The common electrode of the first transistor may be connected to the first power supply input.
The control electrode of the third transistor may be connected to a bias voltage input. As an alternative, the control electrode of the third transistor may be connected to the second power supply input. As a further alternative, the control electrode of the third transistor may be connected to the second input.
The control electrodes of the first and second transistors may be connected to the output electrode of a fifth transistor of the second conduction type whose common electrode is connected to the second power supply input and whose control electrode is connected to the second input.
The control electrodes of the first and second transistors may be connected to the output electrode of a fifth transistor of the second conduction type whose common electrode is connected to the second power supply input, the control electrodes of the third and fifth transistors being connected to an active low gating input.
The voltage follower input may be connected to the first input via the main conduction path of a sixth transistor of the second conduction type whose control electrode is connected to an active high gating input.
The common electrode of the second transistor may be connected to the second input via the main conduction path of a seventh transistor of the second conduction type whose control electrode is connected to the active high gating input.
The common electrode of the second transistor and the control electrode of the third transistor may be connected to the output electrode of an eighth transistor of the first conduction type whose control electrode is connected to the active high gating input.
Each of the transistors may comprise a field effect transistor and the output, control and common electrodes may comprise drain, gate and source electrodes, respectively. Each of the transistors may comprise an amorphous silicon thin film transistor. As an alternative, each of the transistors may comprise a poly-silicon thin film transistor. The shifter may comprise at least part of a CMOS integrated circuit.
According to a second aspect of the invention, there is provided a poly-silicon display comprising an integrated driver including a shifter according to the first aspect of the invention where each of the transistors comprises a poly-silicon thin film transistor.
It is thus possible to improve the performance of a level shifter. In particular, one or more of the following advantages may be achieved:
(a) greater sensitivity permitting operation with very low input voltages;
(b) more robustness to process variation:
(c) lower power consumption resulting from improved logic level voltages:
(d) guaranteed to work in one polarity if the N-type threshold voltages are low;
(e) can be gated or enabled by a single signal;
(f) can be embodied by transistors of similar size.